1. Field
Example embodiments relate to semiconductor integrated circuits controlling synchronous burst read data of non-volatile memories. Also, example embodiments relate to semiconductor integrated circuits controlling data output timing of data output units, non-volatile memory devices including semiconductor integrated circuits controlling synchronous burst read data and/or data output timing of data output units, and/or memory and/or computing systems including semiconductor integrated circuits controlling synchronous burst read data and/or data output timing of data output units.
2. Description of Related Art
In relation to synchronous burst read operations of non-volatile memories, time relationships typically are prescribed between a clock signal and output data.
FIG. 3 is a related art pulse row showing a time relationship between a clock signal and output data. Referring to FIG. 3, data may be confirmed when a burst access time tBA elapses, after a first external clock signal CLK rises, in a case of output data. Additionally, data may be kept maintained during a data hold time tBDH, after the data is confirmed and before the next external clock signal CLK rises.
FIG. 4 is a related art table illustrating relationships between frequency of an external clock signal CLK, burst access time tBA, and/or data hold time tBDH. Referring to FIG. 4, when a clock frequency is 54 MHz, the maximum value of a burst access time tBA may be 14.5 nanoseconds (ns) and/or the minimum value of a data hold time tBDH may be 4 ns. Additionally, when a clock frequency is 108 MHz, the maximum value of a burst access time tBA may be 7 ns and/or the minimum value of a data hold time tBDH may be 2 ns. The above related art table also may show recommended latency for each clock frequency.
FIG. 5 is a related art block diagram illustrating a relationship between a data output unit and a clock signal during a synchronous burst read operation. Referring to FIG. 5, an external clock signal CLK may be inputted into a clock input buffer 40 through a clock pad 50 of a memory chip. The external clock signal CLK′ outputted from the clock input buffer 40 may be inputted to a burst counter 30-1 and/or a data output driver 30-2 of a data output unit 30. Pipeline data read from a memory array 70 through a burst read operation may be controlled by the external clock signal CLK inputted into the burst counter 30-1 and/or the data output driver 30-2 of the data output unit 30, and/or may be outputted from a data output pad 60 to the external. A mode register 20 may exist on the same memory chip, but may not be related to the data output unit 30.
FIG. 6 is a timing diagram illustrating output timing of output data. In FIG. 6, a reference symbol “∘” represents a burst access time tBA and/or a data hold time tBDH of output data outputted from the data output pad 60 of FIG. 5 with respect to each clock frequency. Commonly, it may be designed to achieve the maximum timing margin with respect to the maximum clock frequency. Because of this, with respect to a clock frequency of 108 MHz, a data hold time tBDH and/or a burst data access tBA may be designed to be 4.5 ns, which may be an average value of the minimum value of 2 ns in a data hold time tBDH and the maximum value of 7 ns in a burst access time tBA. Therefore, the maximum timing margin may be achieved.
If a clock frequency becomes lower, for example, due to the above property, there may be only a timing margin of 0.5 ns with respect to the minimum value of 4 ns in a data hold time tBDH at 54 MHz. Thus, system design of a memory may be faced with some difficulties. Conventional art discloses an intention of optimizing the timing of output data through a delayed locked loop (DLL) circuit (that may include a phase comparison circuit, comparing phases between an internal clock and a delay clock, and a variable delay additional circuit, adjusting delay amounts through a signal from the phase comparison circuit). However, this DLL circuit may have a large scale such that it may be difficult to reduce a chip size and/or its power consumption may be relatively high.